Defects that cause decrease in yield in a manufacturing process of a semiconductor integrated circuit are classified roughly into a random defect mainly due to a manufacturing apparatus and particles generated in a process and a systematic defect due to process variations. The random defect and the systematic defect are different in countermeasure contents for a process modification. Therefore, it is important to evaluate which one of the random defect and the systematic defect increases when the number of defects increases for efficiently keeping the yield high.
In Non-Patent Document 1 (Y. Sato et al. “Defect criticality index (DCI): a new methodology to significantly improve DOI sampling rate in 45 nm production environment”: Proc. of SPIE Vol. 6922, 692213 (2008)), a method called DBB (Design Based Binning) in which a defect is classified based on a background pattern (local pattern) of the defect is introduced. The systematic defect includes many defect types having high pattern dependency, such as, a danger point due to OPE (Optical Proximity Effect). On the other hand, the random defect has little pattern dependency. Therefore, when generated defects are classified while concentrating on a specific pattern as a result of the classification based on the DBB, it is possible to determine that the systematic defect inherent in this pattern is generated.